1. Field of the Invention
The present invention relates to an imaging device.
2. Description of the Related Art
As imaging devices using a ramp type AD converter according to the prior art, a configuration described in Japanese Unexamined Patent Application No. 2006-340044 or Japanese Unexamined Patent Application No. 2010-93641 is known. First, a configuration and operations of the imaging device according to the prior art will be described.
FIG. 4 illustrates a schematic configuration of an imaging device using a ramp type AD converter according to the prior art. An imaging device 1001 includes an imaging section 1002, a vertical selecting section 1012, a horizontal selecting section 1014, a column processing section 1015, a reference signal generating section 1016, an output section 1017, and a timing control section 1020.
The timing control section 1020 controls sections such as the vertical selecting section 1012, the horizontal selecting section 1014, the column processing section 1015, the reference signal generating section 1016, and the output section 1017. The imaging section 1002 has a configuration in which a plurality of unit pixels 1003 having a photoelectric conversion element are arranged in the form of a matrix. The unit pixel 1003 generates a pixel signal corresponding to an amount of incident electromagnetic waves and outputs a pixel signal to a vertical signal line 1013 provided for each column.
The vertical selecting section 1012 controls a row address or row scanning of the imaging section 1002 through a row control line 1011 when each of the unit pixels 1003 of the imaging section 1002 is driven. The horizontal selecting section 1014 controls a column address or column scanning of a column AD converting section 1030 of the column processing section 1015.
The column processing section 1015 includes the column AD converting section 1030 provided for each column of the imaging section 1002. The column AD converting section 1030 converts an analog signal, which is a pixel signal output from each of the unit pixels 1003 of the imaging section 1002 to each column, into digital data and outputs the converted data. The reference signal generating section 1016 includes, for example, an integration circuit and a DAC circuit, and generates a reference signal whose level is changed in an inclined shape with the passage of time.
Next, a configuration of the column AD converting section 1030 will be described. All of the column AD converting sections 1030 are configured to be substantially the same, and each of the column AD converting sections 1030 includes a comparison section 1031 and a measurement section 1032.
The comparison section 1031 is a comparator circuit that has a generally well-known differential amplifier as a basic configuration. The comparison section 1031 compares the pixel signal output from the unit pixel 1003 of the imaging section 1002 with the reference signal. For example, when the reference signal is greater than the pixel signal, a High level is output. For example, when the reference signal is smaller than the pixel signal, a Low level is output.
The measurement section 1032 includes an up/down counter circuit, measures a comparison time from when the comparison section 1031 starts comparison until the comparison ends, and generates data corresponding to the comparison time. Accordingly, data corresponding to a size of the pixel signal is obtained. The horizontal selecting section 1014 includes a shift register or a decoder, and controls a column address or column scanning of each the column AD converting section 1030 in the column processing section 1015. Accordingly, the AD converted digital data sequentially passes through a horizontal signal line and is output to the output section 1017.
Next, an AD conversion operation will be described. A specific operation of the unit pixel 1003 will not be described, but a reset level and a signal level are output from the unit pixel 1003 as the pixel signal.
First, after the reset level read from the unit pixel 1003 is stabilized, voltages of two input terminals of the differential amplifier constituting the comparison section 1031 are reset. Then, the comparison section 1031 compares the reference signal with the reset level and ends the comparison process at a timing at which the reference signal satisfies predetermined conditions for the reset level. The measurement section 1032 performs measurement of the comparison time in a down-count mode. A measurement value when the comparison process ends becomes digital data of the reset level.
Next, when the signal level is read from the unit pixel 1003, a reset operation in the comparison section 1031 is not performed. After the signal level read from the unit pixel 1003 is stabilized, the comparison section 1031 compares the reference signal with the signal level, and ends the comparison process at a timing at which the reference signal satisfies predetermined conditions for the signal level. The measurement section 1032 performs measurement of the comparison time in an up-count mode. A measurement value when the comparison process ends becomes digital data of a signal component (a signal obtained by subtracting the reset level from the signal level).
FIG. 5 illustrates a specific circuit configuration of the comparison section 1031 according to the prior art. The comparison section 1031 includes a differential amplifier AMP, capacitive elements C1 and C2, and transistors P6 and P7.
The differential amplifier AMP includes transistors N1 and N2 composed of an NMOS to which a source is commonly connected, transistors P3 and P4 composed of a PMOS that is connected between drains of the transistors N1 and N2 and power VDD and to which a gate is commonly connected, and a current source N5 of an NMOS that is connected between a node commonly connected to sources of the transistors N1 and N2 and a ground GND.
The transistors P6 and P7 composed of a PMOS are connected between gates and drains of the transistors N1 and N2. The transistors P6 and P7 serve as a reset section configured to set an ON state when a reset pulse Reset of Low active is supplied from the timing control section 1020 to each gate, connect gates and drains of the transistors N1 and N2, and reset voltages of gates of the transistors N1 and N2, that is, voltages of two input terminals (a first input terminal IN1 and a second input terminal IN2) of the differential amplifier.
First terminals of the capacitive elements C1 and C2 for cutting a DC level are connected to gates of the transistors N1 and N2, respectively. A second terminal of the capacitive element C1 is supplied with a reference signal Ramp from the reference signal generating section 1016. The second terminal of the capacitive element C2 is supplied with a pixel signal Pixel output from each of the unit pixels 1003 of the imaging section 1002. In addition, a gate of the current source N5 is supplied with a bias voltage Vbias for controlling a current value.
When a plurality of ramp type AD converters represented by a column parallel ramp type AD converter of a CMOS image sensor are configured, the plurality of AD converters share the reference signal. Therefore, when the reference signal is changed due to an influence from a comparison circuit (the comparison section 1031 of FIG. 4) according to an operation of a certain AD converter, other AD converters receive the influence and errors occur in an AD conversion result.
FIG. 6 schematically illustrates an example of an image captured by a CMOS image sensor. The image illustrated in FIG. 6 illustrates an example in which bright regions (regions R0 and R2) and a dark region (a region R1) are mixed. In this example, a signal indicating a comparison result in a comparison circuit is inverted earlier in the region R1 than in the region R2. When the signal indicating the comparison result of the region R1 is inverted earlier, the reference signal is changed due to feedthrough (kickback) from the comparison circuit of the region R1, and errors occur in an AD conversion result of a column of the bright region (the region R2, and particularly, a portion adjacent to the region R1). As a result, image quality is degraded.
As a method of addressing this influence, the following methods are considered.
I) A method in which a buffer circuit represented by a source follower circuit is added to an input of each comparison circuit.
II) A method in which an output impedance of a reference signal generating section (a DAC circuit thereof) is decreased.
In the method I), when the buffer circuit is added to the input of each comparison circuit, an error factor transmitted from the comparison circuit to the reference signal is reduced due to an isolation capability of the buffer circuit.
In the method II), a resistance value of the DAC circuit decreases. As a result, a current value of a current source necessary for generating the same reference signal (for example, a reference voltage of 1 [V]) increases. Therefore, a consumption current increases.